Electronics world

A basic Flip-Flop circuit can be constructed in two ways. • Using two NOR gates • Using two NAND gates We know that a flip-flop circuit consists of two inputs set(S) and reset(R), two outputs Q and Q’. A cross coupled connection is given between output of one gate and the input of the other gate. Such type of cross coupled connection constitutes the feedback path for the flip-flops. These flip-flops are called direct coupled RS Flip flops (or) SR latch. Now to analyze the circuit let us assume that the 1) SET input = 1 and RESET input = 0. For convenience let the Set input be S and Reset input be R. We know that if any input of NOR gate is 1 then its output is 0. Therefore when S=1, the output of the gate corresponding to S (Gate 2 in figure) becomes 0. So Q’ becomes 0. This Q’ is given as an input (Cross coupled connection) along with R to the other gate. So the output of the second gate, Q becomes 1(since both R and Q’ are 0). Conclusion 1: When S=1 and R=0. The outputs Q’=0 and Q=1. Now when the set input(S) returns to 0, the output remains the same. This is because the output of gate 1 (ie) Q is 1.Now the inputs to gate 2 are S=0 and Q=1. So from the truth table of NOR gate we can say that Q’=0.

The fundamental latch is the simple SR flip-flop (also commonly known as RS flip-flop), where S and R stand for set and reset, respectively. It can be constructed from a pair of cross-coupled NAND or NOR logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S is pulsed high while R is held low, then the Q output is forced high, and stays high even after S returns low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low even after R returns low.

It can be seen that when both inputs S = "1" and R = "1" the outputs Q and Q can be at either logic level "1" or "0", depending upon the state of inputs S or R BEFORE this input condition existed. However, input state R = "0" and S = "0" is an undesirable or invalid condition and must be avoided because this will give both outputs Q and Q to be at logic level "1" at the same time and we would normally want Q to be the inverse of Q. However, if the two inputs are now switched HIGH again after this condition to logic "1", both the outputs will go LOW resulting in the flip-flop becoming unstable and switch to an unknown data state based upon the unbalance. This unbalance can cause one of the outputs to switch faster than the other resulting in the flip-flop switching to one state or the other which may not be the required state and data corruption will exist. This unstable condition is known as its Meta-stable state.

Then, a bistable latch is activated or Set by a logic "1" applied to its S input and deactivated or Reset by a logic "1" applied to its R. The SR Latch is said to be in an "invalid" condition (Meta-stable) if both the Set and Reset inputs are activated simultaneously.

The truth Table of AND gate is given below

Flip Flop

• flip-flop is a term referring to an electronic circuit (a bistable multivibrator) that has two stable states and thereby is capable of serving as one bit of memory

• The term flip-flop has come to mostly denote non-transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches

• Flip-flops are heavily used for digital data storage and transfer and are commonly used in banks called "registers" for the storage of binary numerical data

• A flip-flop is usually controlled by one or two control signals and/or a gate or clock signal

• The output often includes the complement as well as the normal output. As flip-flops are implemented electronically, they require power and ground connections