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Tunnel Diode  

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In a conventional semiconductor diode, conduction takes place while the p–n junction is forward biased and blocks current flow when the junction is reverse biased. This occurs up to a point known as the “reverse breakdown voltage” when conduction begins (often accompanied by destruction of the device). In the tunnel diode, the dopant concentration in the p and n layers are increased to the point where the reverse breakdown voltage becomes zero and the diode conducts in the reverse direction. However, when forward-biased, an odd effect occurs called “quantum mechanical tunnelling” which gives rise to a region where an increase in forward voltage is accompanied by a decrease in forward current. This negative resistance region can be exploited in a solid state version of the dynatron oscillator which normally uses a tetrode thermionic valve (or tube). The tunnel diode showed great promise as an oscillator and high-frequency threshold (trigger) device since it would operate at frequencies far greater than the tetrode would, well into the microwave bands. Applications for tunnel diodes included local oscillators for UHF television tuners, trigger circuits in oscilloscopes, high speed counter circuits, and very fast-rise time pulse generator circuits. The tunnel diode can also be used as low-noise microwave amplifier.[4] However, since its discovery, more conventional semiconductor devices have surpassed its performance using conventional oscillator techniques. For many purposes, a three-terminal device, such as a field-effect transistor, is more flexible than a device with only two terminals. Practical tunnel diodes operate at a few millamperes and a few tenths of a volt, making them low-power devices.[5] The Gunn diode has similar high frequency capability and can handle more power.

The tunnel diode showed great promise as an oscillator and high-frequency threshold (trigger) device since it would operate at frequencies far greater than the tetrode would, well into the microwave bands.

And Gate  

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Stylissimo Wordpress Theme

  • Name : Stylissimo
  • Author : Dryicons
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DryIcons presents its second free template, called "Stylissimo". This template is carefully designed following the most basic design rules: style, simplicity and functionality. It can be used as a personal blog, where users could showcase their portfolio to the world, share design-related resources and inspiration and communicate with other designers. "Stylissimo" can also be used as a unique magazine theme, with lots of inspirational portfolios, tutorials, resources and freebies. "Stylissimo" is a three-column template with clear separation of the header, footer and the main container. The HTML/CSS code is well structured and commented which will make your implementation very easy. Initially available as a plain HTML/CSS and as a WordPress theme.

Diodes  

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A basic Flip-Flop circuit can be constructed in two ways. • Using two NOR gates • Using two NAND gates We know that a flip-flop circuit consists of two inputs set(S) and reset(R), two outputs Q and Q’. A cross coupled connection is given between output of one gate and the input of the other gate. Such type of cross coupled connection constitutes the feedback path for the flip-flops. These flip-flops are called direct coupled RS Flip flops (or) SR latch. Now to analyze the circuit let us assume that the 1) SET input = 1 and RESET input = 0. For convenience let the Set input be S and Reset input be R. We know that if any input of NOR gate is 1 then its output is 0. Therefore when S=1, the output of the gate corresponding to S (Gate 2 in figure) becomes 0. So Q’ becomes 0. This Q’ is given as an input (Cross coupled connection) along with R to the other gate. So the output of the second gate, Q becomes 1(since both R and Q’ are 0). Conclusion 1: When S=1 and R=0. The outputs Q’=0 and Q=1. Now when the set input(S) returns to 0, the output remains the same. This is because the output of gate 1 (ie) Q is 1.Now the inputs to gate 2 are S=0 and Q=1. So from the truth table of NOR gate we can say that Q’=0.

 

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SR NAND Gate Flip-Flop  

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The fundamental latch is the simple SR flip-flop (also commonly known as RS flip-flop), where S and R stand for set and reset, respectively. It can be constructed from a pair of cross-coupled NAND or NOR logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S is pulsed high while R is held low, then the Q output is forced high, and stays high even after S returns low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low even after R returns low.

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The Set State Consider the circuit shown above. If the input R is at logic level "0" (R = 0) and input S is at logic level "1" (S = 1), the NAND Gate Y has at least one of its inputs at logic "0" therefore, its output Q must be at a logic level "1" (NAND Gate principles). Output Q is also fed back to input A and so both inputs to the NAND Gate X are at logic level "1", and therefore its output Q must be at logic level "0". Again NAND gate principals. If the Reset input R changes state, and now becomes logic "1" with S remaining HIGH at logic level "1", NAND Gate Y inputs are now R = "1" and B = "0" and since one of its inputs is still at logic level "0" the output at Q remains at logic level "1" and the circuit is said to be "Latched" or "Set" with Q = "1" and Q = "0". Reset State In this second stable state, Q is at logic level "0", Q = "0" its inverse output Q is at logic level "1", not Q = "1", and is given by R = "1" and S = "0". As gate X has one of its inputs at logic "0" its output Q must equal logic level "1" (again NAND gate principles). Output Q is fed back to input B, so both inputs to NAND gate Y are at logic "1", therefore, Q = "0". If the set input, S now changes state to logic "1" with R remaining at logic "1", output Q still remains LOW at logic level "0" and the circuit's "Reset" state has been latched. Operation SR NAND Gate Flip-Flop
SR Flip-Flop operation (BUILT WITH NAND GATES)
Characteristic table Exitation table
S R Action Q(t) Q(t+1) S R Action
0 0 Keep state 0 0 0 X No change
0 1 Q = 0 1 0 0 1 reset
1 0 Q = 1 0 1 1 0 set
1 1 Race Condition 1 1 X 0 No change
X denotes a Don't care condition; meaning the signal is irrelevant

It can be seen that when both inputs S = "1" and R = "1" the outputs Q and Q can be at either logic level "1" or "0", depending upon the state of inputs S or R BEFORE this input condition existed. However, input state R = "0" and S = "0" is an undesirable or invalid condition and must be avoided because this will give both outputs Q and Q to be at logic level "1" at the same time and we would normally want Q to be the inverse of Q. However, if the two inputs are now switched HIGH again after this condition to logic "1", both the outputs will go LOW resulting in the flip-flop becoming unstable and switch to an unknown data state based upon the unbalance. This unbalance can cause one of the outputs to switch faster than the other resulting in the flip-flop switching to one state or the other which may not be the required state and data corruption will exist. This unstable condition is known as its Meta-stable state.

Then, a bistable latch is activated or Set by a logic "1" applied to its S input and deactivated or Reset by a logic "1" applied to its R. The SR Latch is said to be in an "invalid" condition (Meta-stable) if both the Set and Reset inputs are activated simultaneously.

The truth Table of AND gate is given below

My Caption
input A input B output Q
0 0 0
0 1 0
1 0 0
1 1 1

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